1. Field of Invention
This invention relates in general to a method for manufacturing an integrated circuit component, and more particularly to a method of manufacture and structure for a masked ROM unit.
2. Description of Related Art
Read only memory (ROM) is generally formed from a plurality of memory cell units. Each memory cell unit is actually a metallic-oxide-semiconductor field effect transistor (MOSFET). Through suitable adjustment of the threshold voltage of the field effect transistor by an ion implantation operation, the ON/OFF state of the memory unit can be tailored, and as a result, can serve a coding purpose.
Referring to FIGS. 1 through 3, FIG. 1 is a top view of a conventional ROM unit, FIG. 2 is a cross-sectional view taken along line A--A in FIG. 1, showing a section in the direction in which conducting carriers travel along the memory cell unit and FIG. 3 is a cross-sectional view taken along line B--B in FIG. 1, where line A--A and line B--B are approximately perpendicular to each other. Each memory cell unit includes a semiconductor substrate 10, for example, an N-type or a P-type silicon substrate, with field oxide layers 12 already formed above acting as isolating barriers between individual components. An active region 100 is formed above the substrate between the field oxide layers. A gate oxide layer 14 is formed between the field oxide layers 12. A gate terminal structure 16 is located on the gate oxide layer 14 in the active region 100. Source/drain terminals 18 are formed on substrate 10 beneath the gate oxide layer located on each side and at a level below the gate terminal structure 16 in the active region. A channel region 20 is located on the substrate 10 between the source and the drain terminals 18.
In general, the production of ROM can be carried on up to the stage shown in FIG. 2 and FIG. 3. Thereafter, production is delayed until a relevant piece of program code is submitted from the customer. Once the program code has arrived, corresponding programming masks can be manufactured, and then subsequent coding implantation is performed which conditions the threshold voltages of the respective channel regions 20 of the transistors into either an ON or an OFF state, representing a "1" or a "0" state in a binary level logic system.
Because of the restrictions imposed by the design rules on ROM production, as well as the lack of any technological breakthroughs in the manufacturing of integrated circuits, the degree of possible further dimensional reduction of a single transistor binary level logic system is quite limited. Therefore, memory transistors capable of being encoded with three or more levels would be beneficial. However, the number of corresponding coding operations necessary for coding the transistors increases according to the number of levels such multiple stage memory units are designed to have, which increases the production period and consequently lowers the competitiveness of the resulting product.